Device packaging advances are making it nearly impossible to access device leads on PC boards. For example, new advances have allowed for high primary input/output (I/O) pin count on an application specific integrated circuit (ASIC), but allow for no observability of the connections between the ASIC and board it is used on. Level sensitive scan design, for example, boundary scan, has emerged as a way to solve the increasing difficulty in testing packaged devices. Boundary scan methodology is based on a formally adopted IEEE/ANSI standard, IEEE/ANSI 1149.1-1990. This design-in test technique provides virtual access to devices and allows for simplified pattern generation to detect and diagnose structural board faults.
Most design test techniques utilize some form of serial scan test path. At the ASIC level, design test of device logic 14 on the ASIC 10, as shown in FIG. 1, may be accomplished with the use of level sensitive scan design style flip-flops (not shown). The flip-flops are connected together to form one serial scan chain and there may be several serial scan chains or test paths on an ASIC. When all the flip-flops in the ASIC are scannable, testing of the device logic of the ASIC is simplified. A vector pattern or input test data is scanned into the serial scan chain(s). One system clock is applied and the resulting output test data is scanned out of the serial scan chain(s). Scan testing results in very high fault coverage. This is especially important on large ASICs. Scan testing further allows the use of other third party test pattern generation tools to create test vectors.
At the system level, for example, at a board level including several ASICs as shown in FIG. 1, scanning in and out test data is used to test the device logic 15 of the ASICs 10 and the interconnects therebetween. The number of test pins needed to access the board is minimized. The term `boundary scan` has come to describe the serial scan path that is associated with testing of the input/output latches on an ASIC 10, FIG. 1, and, therefore, its interconnects as well. Boundary scan provides test access to device pins 12 by associating a serial shift registry element, or scan cell 14, with each signal pin 12. The boundary scan cells 14 are linked together to form a shift register chain around the device boundary. These scan cells 14 can then be used to control and observe the device pins 12. Each ASIC 10 on the board may have its test data out pin (TDO) connected to the test data in pin (TDI) of the next ASIC in the chain. This creates a daisy chain serial connection of all the ASICs 10 on the board and, therefore, when scanning in a test pattern, all of an ASIC's test data is scanned in at one time.
The boundary scan standard, IEEE/ANSI 1149.1-1990, entirely incorporated herein by reference thereto, is a collection of design rules applied principally at the integrated circuit (IC) level. This standard makes it possible to employ software to control the growing cost of designing and producing digital systems. The primary benefit of this standard is its ability to transform extremely difficult printed circuit board testing problems into well-structured problems that software can solve easily and swiftly. Adhering to this standard enables the purchase of both third party hardware testers and software that will automatically generate test patterns to test the ICs.
Boundary scan is similar to the scan methodology described above using level sensitive scan design type flip-flops. The difference is that, as the name infers, the scan circuitry is associated with flip-flops that make up the ASIC's boundary, i.e., primary in and out flip-flops. All of the boundary flip-flops on each ASIC are connected together into a serial scan test path. The test patterns are shifted into each ASIC under control of test access port (TAP) controller 16 clocked by a test clock input (TCK). After the test patterns are shifted into the serial scan test paths, one test clock cycle is applied and the resulting output data is shifted out of the serial scan path under control of the test access port controller. Upon checking the response data, faults can be detected. The TAP controller provides the necessary clock, data, and control function needed to use the serial scan paths for testing. A TAP controller 16 is designed and built into each ASIC.
For ASIC level testing or fabrication testing, the ASIC device logic is tested using level sensitive scan techniques as described above. Such fabrication testing of the device logic does not require the use of the TAP controller 16 as the test is run using the system clock utilized by the computer system of which the ASIC is a part.
In prior systems designed using level sensitive scan design techniques, the test logic including the TAP controller 16 and associated test logic such as the boundary scan cells and other associated registers, is not entirely tested at the fabrication stage. Such fabrication testing of the test logic was cost and time prohibitive and problematic because of a gated clock problem. Level sensitive scan design is a dual latched based technology, wherein the two latches each need their own nonoverlapping clock pulses for proper gating of signals throughout the system. The TAP controller of level sensitive scan designs generates several signals utilized as clock signals for various types of registers in the test logic. Since these clock signals utilized for clocking are generated by the internal test logic, they are considered gated clocks and such clocks could not be utilized for scanning test patterns into the test logic for fabrication testing thereof. Without fabrication testing of the test logic at the ASIC level, when subsequent testing procedures are performed, it is not known whether the test logic or other logic/interconnects are faulted if a fault is detected.
For this reason, and for other reasons stated below, which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for enhancements to allow for fabrication testing of the test logic of a level sensitive scan design. By providing the ability to perform fabrication testing of the test logic without making any substantial changes in the way that the ASIC device logic is fabrication tested, fabrication testing could be performed with little time and cost. Such fabrication testing of the test logic would allow the purchaser of such ASICs to be assured that the ASICs are entirely substantially free of defect.